This application claims priority from Japanese Patent Application Number JP 2006-292234 filed Oct. 27, 2006, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device which can reduce a resistance in a flip chip mounting.
2. Description of the Related Art
In many discrete semiconductor devices (semiconductor chips), electrodes, respectively connected to an input terminal and an output terminal, are each provided to a different surface of the main surfaces (top surface and bottom surface) of the chip. On the other hand, also known has been a structure that makes a flip chip mounting possible by providing, on one main surface of the chip, a source electrode and a drain electrode respectively connected to an input terminal and an output terminal as well as a gate electrode connected to a control terminal in a MOSFET, for example. This technology is described, for instance, in Japanese Patent Application Publication No. 2002-368218.
Moreover, in another known structure, two MOSFETs are integrated into one chip while sharing a drain terminal, and source electrodes and gate electrodes are provided on one main surface of the chip. In this case, the mounting method is not limited to the flip chip mounting. Nevertheless, since the source electrodes of the two MOSFETs are respectively connected to the input terminal and the output terminal, the electrodes connected to an input terminal and an output terminal are provided on the one main surface of the chip as in the case of Japanese Patent Application Publication No. 2002-368218. This technology is described, for instance, in Japanese Patent Application Publication No. 2002-118258 (especially refer to FIG. 5 thereof).
With reference to FIG. 9, description will be given of a semiconductor device in which two MOSFETs are integrated into one chip as an example of the semiconductor device provided, on one main surface thereof, with an input terminal and an output terminal.
FIG. 9 is a plan view of a semiconductor device 30 which is formed by integrating a first MOSFET 31 and a second MOSFET 32 into one chip. To each of the MOSFETs 31 and 32, a source electrode and a gate pad electrode are connected. A first source electrode 35 and a first gate pad electrode 33 are for the MOSFET 31 while a second source electrode 36 and a second gate pad electrode 34 are for the MOSFET 32.
The two MOSFETs share a substrate (drain region). The first MOSFET 31 and the second MOSFET 32 are arranged, for example, in line symmetry about the center line X-X of the chip. The first gate pad electrode 33 and the second gate pad electrode 34 are independently disposed to the corners of the chip.
The first source electrode 35 and a first source bump electrode 35b, which are connected to a first source terminal S1, are provided on a first main surface Sf1 of the chip. The second source electrode 36 and a second source bump electrode 36b, which are connected to a second source terminal S2, are also provided on the first main surface Sf1. Similarly, the first gate pad electrode 33 and a first gate bump electrode 33b, which are connected to a first gate terminal G1, are provided on the first main surface Sf1. The second gate pad electrode 34 and a second gate bump electrode 34b, which are connected to a second gate terminal G2, are also provided on the first main surface Sf1.
In this case, a drain electrode is shared by the two MOSFETs 31 and 32 and not led out to the outside. A current path is formed by a control signal which is applied to gate electrodes of the two MOSFETs 31 and 32 and by the potential difference applied to each of the first source electrode 35 and the second source electrode 36. Specifically, the first source bump electrode 35b is an electrode connected to the input terminal (or the output terminal) of the MOSFET 30 while the second source bump electrode 36b is an electrode connected to the output terminal (or the input terminal) of the MOSFET 30.
FIG. 10 shows a schematic view of a current path when an electrode (for example, a source electrode S) connected to an input terminal IN and an electrode (for example, a drain electrode D) connected to an output terminal OUT are provided on a first main surface Sf1 of a discrete semiconductor MOSFET as in the case of Japanese Patent Application Publication No. 2002-368218.
A substrate is formed by stacking a low-concentration semiconductor layer LS on a high-concentration semiconductor substrate HS, and an element region e of the MOSFET is provided in the surface of the low-concentration semiconductor layer LS.
In the structure where the source electrode S and the drain electrode D are provided on the first main surface Sf1 of the chip, a current path CP′ is mainly formed from the source electrode S on the first main surface Sf1 to the low-concentration semiconductor layer LS then to the high-concentration semiconductor substrate HS, back to the low-concentration semiconductor layer LS, and then to the drain electrode D. In other words, the current path CP′ includes first current paths CP1′, which are components mainly in vertical directions of the substrate, and a second current path CP2′, which is a component mainly in a horizontal direction of the substrate. Accordingly, the resistance of the current path CP′ from the source electrode S to the drain electrode D of the MOSFET is obtained by combining resistances Ra and Rc in the vertical directions of the substrate and a resistance Rb in the horizontal direction of the substrate.
For example, when a metal layer is formed on a second main surface Sf2 in the structure shown in FIG. 10, the current path in the horizontal direction is formed in or near the metal layer, which has a low resistance. Thereby, the resistance Rb in the horizontal direction can be reduced. However, in a bear chip or the like with which the flip chip mounting is performed, when a metal layer is not formed on the second main surface Sf2, the second current path CP2′ is formed mainly in the high-concentration semiconductor substrate (for example, a silicon substrate) HS. Since the resistance of the high-concentration semiconductor substrate HS is higher than that of the metal layer, the resistance Rb in the horizontal direction depends more on the shape of the second current path CP2′.
The shape of the current path in the horizontal direction is determined by the shape of the chip (semiconductor substrate). Particularly, when the planar shape of the chip is approximately rectangular as shown in FIG. 9, the resistance Rb is significantly influenced by this shape.
FIG. 11 schematically shows a second current path of the MOSFET shown in FIG. 9.
In FIG. 11, for example, two of the first source bump electrodes 35b, which are connected to the input terminal, are disposed on the first MOSFET 31. For example, two of the second source bump electrodes 36b, which are connected to the output terminal, are disposed on the second MOSFET 32. Thus, the second current paths CP2′ are formed between the first source bump electrodes 35b and the second source bump electrodes 36b as shown by the arrow.
In the above-described semiconductor device, the planar shape of the chip is rectangular, and the electrodes connected to the input and output terminals are disposed on the first main surface Sf1 of the chip. In the semiconductor device, the longer the length L′ of the second current path CP2′, which is the length between one end and the other end in the direction of a current flow, is, and the narrower the width W′ of the second current path CP2′ is, the larger the resistance Rb in the horizontal direction becomes. This causes a problem that the resistance of the whole device is increased.